Systems and methods capable of controlling multiple data access

ABSTRACT

When receiving request commands from different hosts, a data system generates corresponding phase control signals and access signals based on the formats of each request command. Based on the phase control signals, timing signals corresponding to respect request commands and including a plurality of enabling time slots are generated in a way that only one timing signal includes an enabling time slot at a certain point of time. Next, an access control signal is outputted to a storage device during the enabling time slot of a corresponding timing signal. Therefore, the storage device only needs to respond to one request command at a certain point of time, and multiple data access can be effectively controlled in the data system.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to systems and methods capable ofcontrolling multiple data access, and more particularly, to systems andmethods capable of controlling multiple data access using a built-intiming generator.

2. Description of the Prior Art

In a fast-developing digital world where data systems are widely used,the accuracy and speed when performing data access, data transmission,data storage and data display have to be improved continuously. One ofthe most important factors that influence the performance of a datasystem is data access of the related memory devices. In addition, in ahigh-speed and multi-functional data system, different tasks areallotted to the memory devices so that corresponding processors and thememory devices can function properly. Common data systems can operatebased on a synchronous data access structure or an asynchronous dataaccess structure. In a synchronous data system, a synchronous clock isused for controlling the input/output signals of the memory devices andthe internal control signals of the data system. Therefore, thesynchronous data system can provide high-speed and accurate dataaccesses, as well as reduce the time for executing commands andtransmitting data. On the other hand, an asynchronous data system doesnot require a synchronous clock for performing data access. Instead,data is stored or read when corresponding input signals or commandschange.

The data systems become more and more complicated in order to providemore functions. Regardless of synchronous or asynchronous structures, adata system is often required to receive multiple commands given bydifferent hosts. When receiving request commands given by differenthosts, the data system has to adequately arrange the sequence forexecuting each request command so that each host can access datasuccessfully. Since an asynchronous data system does not have asynchronous clock signal, an arbitration mechanism is required forprioritizing different request commands. Although a synchronous datasystem can arrange the sequence for executing each request command basedon a synchronous clock signal having a constant period, transmitting thesynchronous clock signal consumes large amount of power. In addition,multiple synchronous timing signals, instead of a single synchronoustiming signal, are required in a complicated data system. Whentransmitting signal between the “time zones” of different synchronoustiming signals, frequency and phase variations exist and requestcommands for transmitting signal asynchronously are also required.Therefore, in order to enhance system efficiency, lower powerconsumption and design data systems of larger scales, asynchronous datatransmission without a synchronous timing signal becomes more and moreimportant.

Reference is made to FIG. 1 for a functional diagram illustrating aprioritizing circuit 10 disclosed in U.S. Pat. No. 4,339,808“ASYNCHRONOUS EVENT PRIORITIZING CIRCUIT”. The prioritizing circuit 10includes a latch 12, a latch control 14, a priority logic 16, and adelay circuit 18. The latch 12 receives asynchronous request commandsREQUEST₁ and REQUEST₂ respectively given by two hosts, and generatescorresponding output signals Q1 and Q2 based on a strobe signal S sentfrom the latch control 14. Based on clear signals CLEAR₁, CLEAR₂ and theoutput signals Q1, Q2, the latch control 14 generates the strobe signalS and sends the strobe signal S to the latch 12 and the delay circuit18. The delay circuit 18 generates a delayed strobe signal S′corresponding to the strobe signal S, and sends the delayed strobesignal S′ to the priority logic 16. The priority logic 16 arbitratespriority between the output signals Q1 and Q2 and generatescorresponding grant signals GRANT₁ and GRANT₂ based on the delayedstrobe signal S′ generated by the delay circuit 18. The prior artprioritizing circuit 10 controls multiple data access using the delaycircuit 18 whose characteristics tend to deviate from nominal valueswhen the temperature or the operating voltages vary. Therefore, multipledata access may not be performed accurately and the correctly.

Reference is made to FIG. 2 for a functional diagram illustrating acontrol circuit 20 for asynchronous events disclosed in U.S. Pat. No.6,591,323 “MEMORY CONTROLLER WITH ARBITRATION AMONG SEVERAL STROBEREQUESTS”. The control circuit 20 includes a pool/queue state machineSM1, transaction processor state machines SM2-SM4, bank state machinesSM5-SM8, a command arbitrator 22, a command output flip flop 24, and adynamic random access memory (DRAM) 26. The prior art control circuit 20receives asynchronous request commands given by a plurality hosts viathe pool/queue state machine SM1 and arbitrates priority between theplurality of request commands based on a state mechanism provided by thetransaction processor state machines SM2-SM4 and the bank state machinesSM5-SM8. Since a synchronous timing signal is required as the triggersignal in the state mechanism, the prior art control circuit 20 cannotbe applied in asynchronous data systems.

SUMMARY OF THE INVENTION

The present invention provides a data system capable of controllingmultiple data access comprising a storage device for receiving a controlsignal and an address signal and for accessing data stored at an addresscorresponding to the address signal; a multiple access control devicefor receiving a plurality of request commands given by a plurality ofhosts when attempting to access the storage device, and therebygenerating corresponding phase control signals and access signals basedon the request commands; a timing signal generating device for receivingthe phase control signals generated by the multiple access controldevice and thereby generating a plurality of timing signals each relatedto a corresponding request command and including a plurality of enablingtime slots based on a phase reference signal and a corresponding phasecontrol signal, wherein only a timing signal among the plurality oftiming signals includes an enabling time slot at a certain point oftime; an access control device for receiving the access signals and thetiming signals respectively generated by the multiple access controldevice and the timing signal generating device, and outputtingcorresponding control signals to the storage device during the enablingtime slots of corresponding timing signals; and an address controldevice for receiving the access signals and the timing signalsrespectively generated by the multiple access control device and thetiming signal generating device, and generating a plurality of addresssignals each related to a corresponding access signal.

The present invention also provides a method for controlling multipledata access comprising receiving a plurality of request commands,generating phase control signals and access signals corresponding toeach request command, generating a plurality of timing signals eachrelated to a corresponding request command and including a plurality ofenabling time slots based on a corresponding phase control signal,wherein only a timing signal among the plurality of timing signalsincludes an enabling time slot at a certain point of time, outputtingcorresponding control signals during the enabling time slots ofcorresponding timing signals, and generating a plurality of addresssignals each related to a corresponding access signal, and accessingdata stored in a storage device based on the control signals and thecorresponding address signals.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional diagram of a prior art prioritizing circuit.

FIG. 2 is a functional diagram of a prior control circuit forasynchronous events.

FIG. 3 is a functional diagram of a data system capable of controllingmultiple data access according to the present invention.

FIG. 4 is a signal diagram illustrating a method for controllingmultiple data access in a data system according to a first embodiment ofthe present invention.

FIG. 5 is a signal diagram illustrating a method for controllingmultiple data access in a data system according to a second embodimentof the present invention.

FIG. 6 is a signal diagram illustrating a method for controllingmultiple data access in a data system according to a third embodiment ofthe present invention.

FIG. 7 is a signal diagram illustrating a method for controllingmultiple data access in a data system according to a fourth embodimentof the present invention.

FIG. 8 is a flowchart illustrating a method for controlling multipledata access in a data system according to the present invention.

DETAILED DESCRIPTION

Reference is made to FIG. 3 for a functional diagram illustrating a datasystem 30 capable of controlling multiple data access according to thepresent invention. The data system 30 includes a multiple access controldevice 32, a timing signal generator 34, an access control device 36, anaddress control device 38, a data buffer 44, and a storage device 46.The data system 30 can receive commands given by a plurality of externalsystems, which are represented by a plurality of hosts designated ashost 1 trough host N in FIG. 3. The request commands given by host1-host N when attempting to access data stored in the storage device 46are respectively represented by REQUEST₁-REQUEST_(N). The data system 30receives the request commands REQUEST₁-REQUEST_(N) via the multipleaccess control device 32, which then generates corresponding phasecontrol signals PHASE₁-PHASE_(N), access signals ACCESS₁-ACCESS_(N), anda trigger signal TRIGGER.

The timing signal generator 34 is coupled to the multiple access controldevice 32 and includes a self-excited oscillator 40 and a pulsegenerator 42. After receiving the trigger signal TRIGGER, theself-excited oscillator 40 generates a phase reference signal REF. Basedon the phase reference signal REF and the phase control signalsPHASE₁-PHASE_(N), the pulse generator 42 generates timing signalsCLOCK₁-CLOCK_(N) respectively corresponding to the request commandsREQUEST₁-REQUEST_(N). Each of the timing signals CLOCK₁-CLOCK_(N)includes a plurality of enabling time slots, and only one of the timingsignals CLOCK₁-CLOCK_(N) includes an enabling time slot at a certainpoint of time. The relationship between the timing signalsCLOCK₁-CLOCK_(N) will be described in more detail in the followingparagraphs.

The access control device 36, coupled to the multiple access controldevice 32 and the timing signal generator 34, can receive access signalsACCESS₁-ACCESS_(N) related to the request commands REQUEST₁-REQUEST_(N),and outputs corresponding control signals CONTRL₁-CONTROL_(N)respectively during the enabling time slots of the timing signalsCLOCK₁-CLOCK_(N) to the storage device 46. The address control device38, also coupled to the multiple access control device 32 and the timingsignal generator 34, can receive access signals ACCESS₁-ACCESS_(N)related to the control signals CONTRL₁-CONTROL_(N), and outputs addresssignals ADDRESS₁-ADDRESS_(N) respectively related to the control signalsCONTRL₁-CONTROL_(N) to the storage device 46. The address signalsADDRESS₁-ADDRESS_(N) represent related addresses at which data is to beaccessed based on the request commands REQUEST₁-REQUEST_(N),respectively.

The storage device 46 can include any type of memory, and a dynamicrandom access memory (DRAM) is used for illustrating the presentinvention. After receiving a control signal and its correspondingaddress signal, the storage device 46 accesses data stored at acorresponding address indicated by the address signal. For example, whenthe storage device 46 receives a control signal CONTROL₁ representing arequest command for data read together with its corresponding addresssignal ADDRESS₁, the storage device 46 outputs data stored at an addressindicated by the address signal ADDRESS₁ to the host 1 via the databuffer 44. When the storage device 46 receives a control signal CONTROL₁representing a request command for data write together with itscorresponding address signal ADDRESS₁, the storage device 46 stores datainto an address indicated by the address signal ADDRESS₁ via the databuffer 44.

The request commands given by the hosts have to match a predeterminedprotocol, so that the data system 30 can properly identify the requestcommands and execute corresponding steps. Based on the formats of therequest commands REQUEST₁-REQUEST_(N) given by the host 1-host N, thedata system 30 of the present invention can generate corresponding phasecontrol signals PHASE₁-PHASE_(N) that respectively include informationof each parameter in the request commands REQUEST₁-REQUEST_(N).Therefore, the pulse generator 42 of the timing signal generator 34 canadjust the phase reference signal REF based on the phase control signalsPHASE₁-PHASE_(N) in order to generate the timing signalsCLOCK₁-CLOCK_(N) corresponding to the request commandsREQUEST₁-REQUEST_(N), respectively.

Reference is made to FIG. 4 for a signal diagram illustrating a methodfor controlling multiple data access in the data system 30 according toa first embodiment of the present invention. If the data system 30simultaneously receives the request command REQUEST₁ from the host 1 andthe request command REQUEST₂ from the host 2, the phase reference signalREF, the trigger signal TRIGGER, the timing signals CLOCK₁ and CLOCK₂,and the received request commands REQUEST₁ and REQUEST₂ are illustratedby waveforms of respective namesakes in FIG. 4. At T1 the trigger signalTRIGGER activates the self-excited oscillator 40, which then generatesthe phase reference signal REF. Based on the phase control signal PHASE₁related to the request command REQUEST₁, the phase control signal PHASE₂related to the request command REQUEST₂, and the phase reference signalREF, the pulse generator 42 generates the timing signal CLOCK₁ and thetiming signal CLOCK₂ each including a plurality of enabling time slots.The enabling time slots of the timing signals CLOCK₁ and CLOCK₂ can bethe periods in which respective waveforms have a high level, and arerepresented by E1 and E2 in FIG. 4, respectively. The lengths of theenabling time slots E1 and E2 depend on the formats of the requestcommands REQUEST₁ and REQUEST₂, and only one timing signal includes anenabling time slot at a certain point of time. As a result, when theaccess control device 36 outputs control signals CONTRL₁ and CONTROL₂respectively during the enabling time slots of the timing signals CLOCK₁and CLOCK₂ to the storage device 46, the storage device 46 only respondsto the host 1 or the host 2 at a certain point of time. The presentinvention can thus control multiple data access using the timing signalsincluding a plurality of enabling time slots.

Reference is made to FIG. 5 for a signal diagram illustrating a methodfor controlling multiple data access in the data system 30 according toa second embodiment of the present invention. If the data system 30simultaneously receives the request command REQUEST₁ from the host 1 andthe request command REQUEST₂ from the host 2, the phase reference signalREF, the trigger signal TRIGGER, the timing signals CLOCK₁ and CLOCK₂,and the received request commands REQUEST₁ and REQUEST₂ are alsoillustrated by waveforms of respective namesakes in FIG. 5. In thesecond embodiment of the present invention, the data system 30 hasalready completed the request command REQUEST₁ given by the host 1 at T2and does not receive any request command given by other hosts.Therefore, the timing signal CLOCK₂ includes an enabling time slot thatstarts at T2 and finishes at T3 when the data system 30 has completedthe request command REQUEST₂ given by the host 2.

Reference is made to FIGS. 6 and 7 for signal diagrams illustratingmethods for controlling multiple data access in the data system 30according to a third and fourth embodiments of the present invention. Ifthe data system 30 receives the request command REQUEST₂ from the host 2while executing the request command REQUEST₁ given by the host 1, thephase reference signal REF, the trigger signal TRIGGER, the timingsignals CLOCK₁ and CLOCK₂, and the received request commands REQUEST₁and REQUEST₂ are also illustrated by waveforms of respective namesakesin FIGS. 6 and 7. In the third embodiment of the present invention, T2does not correspond to an integral multiple of the period of the phasereference signal REF, which means the data system 30 cannot terminatethe execution of the request command REQUEST₁ immediately. Therefore,when receiving the request command REQUEST₂ from the host 2 at T2, thedata system 30 continues to execute the request command REQUEST₁ givenby the host 1 until T3, which corresponds to a next integral multiple ofthe period of the phase reference signal REF. Then the timing signalsCLOCK₁ and CLOCK₂ including the enabling time slots E1 and E2 are usedfor controlling multiple data access. Similarly, in the fourthembodiment of the present invention, T2 corresponds to an integralmultiple of the period of the phase reference signal REF, which meansthe data system 30 can terminate the execution of the request commandREQUEST₁ immediately. Therefore, when receiving the request commandREQUEST₂ from the host 2 at T2, the data system 30 can immediatelycontrol multiple data access using the timing signals CLOCK₁ and CLOCK₂including the enabling time slots E1 and E2.

Reference is made to FIG. 8 for a flowchart illustrating steps formultiple data access in the data system 30 according to the presentinvention. The flowchart in FIG. 8 includes the following steps:

Step 810: receive request commands REQUEST₁-REQUEST_(N);

Step 820: generate phase control signals PHASE₁-PHASE_(N) and accesssignals ACCESS₁-ACCESS_(N) respectively corresponding to the requestcommands REQUEST₁-REQUEST_(N);

Step 830: generate timing signals CLOCK₁-CLOCK_(N) including a pluralityof enabling time slots based on the request commandsREQUEST₁-REQUEST_(N) respectively;

Step 840: output control signals CONTROL₁-CONTROL_(N) during theenabling time slots of the timing signals CLOCK₁-CLOCK_(N) respectively;

Step 850: generate address signals ADDRESS₁-ADDRESS_(N) respectivelycorresponding to the request commands REQUEST₁-REQUEST_(N) based on theaccess signals ACCESS₁-ACCESS_(N) respectively; and

Step 860: access data stored in a storage device based on the controlsignals CONTROL₁-CONTROL_(N) and the corresponding address signalsADDRESS₁-ADDRESS_(N).

In the data system of the present invention, the self-excited oscillator40 of the timing signal generator 34 is not activated if no requestcommand is given, thereby reducing power consumption. When receivingrequest commands given by different hosts, the multiple access controldevice 32 activates the self-excited oscillator 40 and generatescorresponding phase control signals based on the formats of the requestcommands. The pulse generator 42 can thus adjust a phase referencesignal generated by the self-excited oscillator 40 based on each phasecontrol signal, and generates timing signals having a plurality ofenabling timing slots. Only one timing signal includes an enabling timeslot at a certain point of time. As a result, the storage device 46 onlyresponds to a request command given by a host at a certain point oftime. The present invention can thus effectively control multiple dataaccess using the timing signals including a plurality of enabling timeslots.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

1. A data system capable of controlling multiple data access comprising:a storage device for receiving a control signal and an address signaland for accessing data stored at an address corresponding to the addresssignal; a multiple access control device for receiving a plurality ofrequest commands given by a plurality of hosts when attempting to accessthe storage device, and thereby generating corresponding phase controlsignals and access signals based on the request commands; a timingsignal generating device for receiving the phase control signalsgenerated by the multiple access control device and thereby generating aplurality of timing signals each related to a corresponding requestcommand and including a plurality of enabling time slots based on aphase reference signal and a corresponding phase control signal, whereinonly a timing signal among the plurality of timing signals includes anenabling time slot at a certain point of time; an access control devicefor receiving the access signals and the timing signals respectivelygenerated by the multiple access control device and the timing signalgenerating device, and outputting corresponding control signals to thestorage device during the enabling time slots of corresponding timingsignals; and an address control device for receiving the access signalsand the timing signals respectively generated by the multiple accesscontrol device and the timing signal generating device, and generating aplurality of address signals each related to a corresponding accesssignal.
 2. The data system of claim 1 further comprising a databuffering device for storing the access signals outputted by themultiple access control device, data to be stored in the storage deviceand data outputted by the storage device.
 3. The data system of claim 1wherein the timing signal generating device comprises: a self-excitedoscillating device for generating the phase reference signal whenreceiving a trigger signal generated by the multiple access controldevice; and a pulse generating device for generating the plurality oftiming signals.
 4. The data system of claim 1 wherein the storage deviceincludes a dynamic random access memory (DRAM).
 5. A method forcontrolling multiple data access comprising the following steps: (a)receiving a plurality of request commands; (b) generating phase controlsignals and access signals corresponding to each request command; (c)generating a plurality of timing signals each related to a correspondingrequest command and including a plurality of enabling time slots basedon a corresponding phase control signal, wherein only a timing signalamong the plurality of timing signals includes an enabling time slot ata certain point of time; (d) outputting corresponding control signalsduring the enabling time slots of corresponding timing signals; (e)generating a plurality of address signals each related to acorresponding access signal; and (f) accessing data stored in a storagedevice based on the control signals and the corresponding addresssignals.
 6. The method of claim 5 wherein step (c) includes generating aplurality of timing signals each related to a corresponding requestcommand and including a plurality of enabling time slots based on aphase reference signal and a corresponding phase control signal.
 7. Themethod of claim 6 further comprising generating the phase referencesignal.
 8. The method of claim 7 further comprising: generating atrigger signal when receiving the request commands; and generating thephase reference signal when receiving the trigger signal.